Multi-stage pipelined analog to digital converters (ADC) provide efficient high speed conversion of analog signals to digital equivalents. A representative multi-stage pipelined ADC 10 is shown in FIG. 1. The ADC 10 generally includes a plurality of converter stages, such as stages 11, 12 and 13, arranged in series relative to each other. Each converter stage operates by comparing an analog input voltage to thresholds provided by reference signals Vretp and Vrefn. As a result, each converter stage provides one or more bits of digital data to a digital correction circuit 15. The digital correction circuit 15, in turn, resolves the digital output from each stage into a digital output 16 that corresponds to an analog input 17.
FIG. 2 is a generalized block diagram of each converter stage. In operation, each stage accepts an analog input voltage and generates a residual analog voltage and a digital stage output. In particular, each stage applies the analog input voltage to a multiplying digital to analog converter (MDAC) 19 to generate the residual analog voltage. The residual analog voltage is then provided to a comparator 18, which generates the digital stage output. The residual analog voltage also serves as input to subsequent converter stages. This arrangement is also referred to herein as a bit-and-one-half analog to digital converter.
Each converter stage may include a switched capacitor circuit as shown in FIG. 3. The switched capacitor circuit operates in accordance with a two cycle clock with phases designated as φ1 and φ2. During a sampling phase, input capacitors C1 and C2 are charged by an input voltage Vin. In this phase, an operational amplifier 21 does not perform a function. During a subsequent integration phase, the switched capacitor circuit generates a residual output voltage. More specifically, the charge stored by the input capacitors is integrated by the operational amplifier 21 to generate an output voltage Vout. In other words, the operational amplifier 21 is active every other clock cycle. The same bias current is continuously supplied to the operational amplifier 21.